1. Field of the Invention
Embodiments generally relate to wafer bonding techniques, and more specifically to a method for manufacturing hetero-bonded wafers for the application of heterogeneous device integration and wafer level packaging.
2. Description of the Related Art
Heterogeneous device integration through the combination of dissimilar materials such as silicon, compound semiconductors, piezoelectric materials, etc., offers the potential to provide versatile functions not available from pure devices alone. One method for heterogeneous device integration has been wafer bonding technology. Wafer bonding techniques readily available today include anodic bonding, thermo-compression boding, eutectic bonding, diffusion bonding, and solder bonding. These conventional wafer bonding techniques require high bonding temperatures ranging from 200° C. to 400° C. Bonding of dissimilar materials having different thermal expansion coefficients (TEC) at such a high temperature gives rise to thermal stresses and strains that lead to defect generation, debonding, bow/warp and cracking.
Wafer bonding techniques are also used for wafer level packaging (WLP). In WLP, silicon is most commonly used as a cap or encapsulation material due to the advanced processing technologies and good mechanical properties. Many kinds of silicon based devices such as accelerometers, FBAR (film bulk acoustic resonator), CMOS image sensors, fluidic devices, and pressure sensors have successfully adopted WLP technology using silicon cap wafer bonding. But, non-silicon based devices made of compound semiconductors and piezoelectric materials have not been successful using silicon cap wafer bonding due to TEC mismatch problems. For instance, Lithium niobate (LiNbO3) and Lithium tantalite (LiTaO3), commonly used for surface acoustic wave (SAW) filter fabrication, have several times larger TEC than silicon or LTCC, thus wafer bonding of silicon and piezoelectric materials has significant thermal stress problems. Therefore, development of a heterogeneous wafer bonding method especially having a large TEC mismatch is very useful for both heterogeneous device integration and WLP.
Room temperature wafer bonding techniques are developed to solve the thermo mechanical stress problems between dissimilar materials. Direct bonding or fusion bonding is a typical example of room temperature wafer bonding techniques. (Reference; J. B. Lasky, “Wafer bonding for silicon-on insulator technologies” Appl. Phys. Lett. 48 (1986) 78., and U. Gösele, M. Alexe, and Q-Y-Tong, “Wafer bonding for materials integration” Compound Semiconductor 6(7) September/October 2000). Direct wafer bonding is a technology that allows wafers to be bonded at room temperature without using any adhesive materials. The bonding strength of direct bonding is relatively weak, therefore the bonded wafer pair usually have to undergo a heat treatment at high temperature for more than several hours to increase the bond strength across the bonding interface. However, serious thermal stress imposed by subsequent heat treatment limits the allowed temperature range and obtainable bond strength.
Attempts to improve the bond strength of the room temperature bonding have been performed by various methods such as wet chemical pre-treatment and high speed ion plasma treatment of bonding surface (Reference; B. Muller, et al, “Tensile strength characterization of low-temperature fusion bonded silicon wafers” J. Micromech, Microeng. I (1991) 161-166, and Q-Y-Tong, et al, “Low temperature wafer direct bonding”, J. Microelectromech. Sys. 3 (1994) 29, and M. Gabriel, B. Johnson, R. Suss, M, Reiche, M. Eichler, “Wafer direct bonding with ambient pressure plasma activation”, Microsyst Technol (2006) 12: 397-400). Surface activated bonding (SAB) was most successful among them by using the method of impinging fast ion beams of Ar, O2, or N2 plasma in very high vacuum to the bonding surfaces to remove oxide on the surfaces. The SAB has been known useful between various materials such as semiconductor-semiconductor, metal-metal, metal-ceramic, and semiconductor-metal. However, one drawback of the SAB is high cost of manufacturing due to the high vacuum level of about 1×10−6 Torr or above.
Although room temperature direct bonding techniques are potentially promising to solve the thermal stress issues for heterogeneous wafer bonding, it has several intrinsic obstacles hard to be overcome. For example, surface cleanness and smoothness are very critical for successful direct bonding, but practically such conditions are hardly to be met in the case of processed wafers having a variety of devices and surface conditions. In addition to the surface conditions, bonding of processed wafers may further require electrical interconnections between devices or circuits carried in the bonding wafers for their functional integration. Therefore, contact pads or solder bumps are required but can produce a significant surface topology problem.
Instead of the wafer bonding method, another approach for heterogeneous device integration of dissimilar materials has been die(or chip)-to-wafer bonding method. In die-to-wafer bonding scheme, the area of bond interface is very small compared to wafer-to-wafer bonding, and the dies and a host wafer are free to expand or contract in lateral directions. Thus wafer scale bow and warp is avoided because the thermo-mechanical stress is confined within the die level. Another advantage of the die-to-wafer bonding is that the bonding temperature can be extended to higher temperature than that of the wafer-to-wafer bonding. However, conventional die-to-wafer bonding method needs complicated manufacturing steps, such as singulating dies from a donor wafer, cleaning dies, and bonding each of the dies onto a receiving wafer, and therefore it is not cost effective.
Thermal stresses and strains caused by the mismatch of TEC are an intrinsic property of materials that cannot be completely solved, but wafer level effects such as bow and warp can be eliminated, and debonding and cracking in die level can be reduced by utilizing the advantage of die-to-wafer bonding scheme, but improving the high cost of manufacturing.